Class Information

Calendar

Projects

Additional Reading

Other Resources

Acknowledgments

Class Information

Instructor: Arjan Durresi (durresi@csc.lsu.edu). TA This graduate course focuses on the techniques of quantitative analysis and evaluation of modern computing systems, such as the selection of appropriate benchmarks to reveal and compare the performance of alternative design choices in system design. The emphasis is on the major component subsystems of high performance computers: pipelining, instruction level parallelism, memory hierarchies, input/output, and network-oriented interconnections. In addition to the textbook, this course includes a number of readings from research papers. The course will involve a semester-long project. Homework Reading will be assigned for each lecture. Before lecture, every student must submit a one page report of the assigned papers (report should contain a one paragraph summary of the paper, description of three strong points of the paper and three weak points of the paper). The reports are due one hour before the class starts (DUE TIME: 12:30 PM), by email, include 7080 and the homework number in the subject. Homework can be submitted by email to me at durresi@byte.csc.lsu.edu, include 7080 - HW# in the subject. IMPORTANT: Submit your homework in PDF format or txt and include in the file's title: 7080, HW#, Your name. Efficient Reading of Papers in Science and Technology Project Every student must complete a project on one of the topics discussed in the class. Students are required to work in teams of two on the project. In addition to the presentation given in the class every team will meet with me to discuss the accomplished results and asses the contribution of each team member. Every project must have a practical component that will require you to do an implementation and demonstration. Textbook John L. Hennessy, David A. Patterson "Computer Architecture: A Quantitative Approach" Third Edition, Morgan Kaufmann, 2002, ISBN: 1558605967 Class Schedule and Office Hours TTh 1:40-03:00pm 241 Lockett hall, Arjan Durresi: Tu 3-4 and Th 3-4 Coates Hall 291 Class Roster

Calendar

Week Tuesday Thursday January 17-21 Course overview and topics 2 slides per page 6 slides per page Readings due Janury 25, 2005: Architecture of the IBM System/360 G.M.Amdahl, G.A.Blaauw, F.P.Brooks, Jr. The Architecture of the Burroughs B5000 - 20 Years Later and Still Ahead of the Times? Alastair J.W. Mayer Introduction to Computer Architecture 2 slides per page 6 slides per page January 24-28 Introduction to Computer Architecture: Instructions 2 slides per page 6 slides per page Readings due February 1, 2005: The Case for te Reduced Instruction Set Computer David A. Patterson, David R. Ditzel Comments on "The Case for te Reduced Instruction Set Computer," By Patterson adn Ditzel Douglas W. Clark, William D. Strecker Introduction to Performance Evaluation 2 slides per page 6 slides per page February 1-4 Processor Data Path and Control 2 slides per page 6 slides per page Readings due February 10, 2005: David Patterson and Carlo Sequin, RISC I: A Reduced Instruction Set VLSI Computer in Proceedings of the International Symposium on Computer Architecture (ISCA) 1981, James Smith and Andrew Pleszkun, Implementation of Precise Interrupts in Pipelined Processors in Proceedings of the International Symposium on Computer Architecture (ISCA) 1985 Gurindar Sohi and Sriram Vajapeyam, Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors in Proceedings of the International Symposium on Computer Architecture (ISCA) 1987 Processor Data Path and Control 2 slides per page 6 slides per page February 7-11 No Class. Mardi Gras Holiday Pipelining 2 slides per page 6 slides per page Readings due February 17, 2005: R. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic units IBM Journal, January 1967 Jack Dennis and David Misunas, A Preliminary Architecture for a Basic Data-Flow Processor Proceedings of the International Symposium on Computer Architecture (ISCA) 1975 Gregory papadopoulos and David Culler, Monsoon: an Explicit Token-Store Architecture Proceedings of the International Symposium on Computer Architecture (ISCA) 1990 February 14-18 Pipelining 2 slides per page 6 slides per page Pipelining 2 slides per page 6 slides per page February 21-25 Memory 2 slides per page 6 slides per page Readings due March 1, 2005: Brian Fields, Shai Rubin, Rastislav Bodik, Focusing Processor Policies via Critical-Path Prediction in Proceedings of the 28th International Symposium on Computer Architecture (ISCA 2001) , James Smith, Decoupled Access/Execute Computer Architectures in Proceedings of the International Symposium on Computer Architectures (ISCA), 1982 Richard Russel, The CRAY-1 Computer System Communications of the ACM, 21(1) 63-72, January 1978 2 slides per page 6 slides per page Readings due March 3, 2005: Subbarao Palacharla, Norman P. Jouppi and J. E. Smith,, Complexity-effective superscalar processors in Proceedings of the 24th International Symposium on Computer Architecture (ISCA). Denver, 1997 , Joseph Fisher, Very Long Instruction Word Architectures and the ELI-512 in Proceedings of the International Symposium on Computer Architecture (ISCA), 1983 Tse-Yu Yeh and Yale Patt, Alternative Implementations of Two-level Adaptive Branch Prediction Proceedings of the International Symposium on Computer Architecture (ISCA), 1992 March 14-18 Memory 2 slides per page 6 slides per page Readings due March 17, 2005: David Kroft, Lockup-Free Instruction Fetch/Prefetch Cache Organization in Proceedings of the International Symposium on Computer Architecture (ISCA), 1981 , Normal Jouppi, Improving Direct-mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch buffers in Proceedings of the International Symposium on Computer Architectures (ISCA), 1981 Memory 2 slides per page 6 slides per page April 4-8 Memory 2 slides per page 6 slides per page Readings due April 12, 2005 (7,13): Aad J. van der Steen, Jack J. Dongarra, Overview of Recent Supercomputers Jack J. Dongarra, Present and Future Present and Future: Supercomputer Architectures and their Interconnects Kimberly Frith Analysis of supercomputer architectures, focusing on speedup choices Cray Links to Supercomputer Architectures Information High Performance Computing: A Short Tour through Supercomputers, Clusters, and Grid Computing QUIZ April 18-22 Interfacing Processors and Peripherals 2 slides per page 6 slides per page Readings due April 21, 2005 (5,11,16): Armando Fox and David Patterson, Self-Repairing Computers, Appears in Scientific American, June 2003 David Patterson, Aaron Brown, et. all, Recovery Oriented Computing (ROC): Motivation, Definition, Techniques, and Case Studies, UC Berkeley Computer Science Technical Report UCB//CSD-02-1175, March 15, 2002. Oppenheimer, D., A. Brown, et. all, ROC-1: Hardware Support for Recovery-Oriented Computing, IEEE Transactions on Computers, vol. 51, no. 2, February 2002. Interfacing Processors and Peripherals 2 slides per page 6 slides per page Readings due April 26, 2005: (1) Todd Mowry, Monica Lam, and Anoop Gupta, Design and Evaluation of a Compiler Algorithm for Prefetching, Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 1992 (2) Subbarao Palacharla and R.E. Kessler, Evaluating Stream Buffers as a Secondary Cache Replacement, , Proceedings of the International Symposium on Computer Architecture (ISCA-21), 1994. (3) B. Ramakrishna Rau, Pseudo-Randomly Interleaved Memory,Proceedings of the International Symposium on Computer Architecture (ISCA-18), 1991 April 25-29 2 slides per page 6 slides per page Readings due April 28, 2005: M. Y. Hsiao, A Class of Optimal Minimum Odd-weight-column SEC-DED Codes IBM J. Res Develop, vol 14, no 4, July 1970 Shigeo Kaneda, A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications,IEEE Transactions on computers, vol c-33, no 8, August 1984 M. Blaum, J. Brady, J. Bruck and J. Menon, EVENODD: an optimal scheme for tolerating double disk failures in RAID architectures Proceedings of the 21st International Symposium on Computer Architecture (ISCA), 1994 2 slides per page 6 slides per page Readings due May 5, 2005: (6) David patterson, Garth Gibson, and Randy Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), ACM SIGMOD conference, 1988 (8) Dean Tullsen, Susan Eggers, and Henry Levy, Simultaneous Multithreading: Maximizing On-Chip Parallelism , Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995 (12) Steve Swanson, Luke McDowell, Michael Swift, Susan Eggers, Henry Levy, An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors, ACM SIGMOD conference, 1988 May 2-6 2 slides per page 6 slides per page 2 slides per page 6 slides per page

Class Projects

Additional Resourses

WWW Computer Architecture Home Page Online version of classic architecture book  Computer structures: readings and examples [Compiled by] C. Gordon. The SimpleScalar simulator is a very flexible simulation package that comes with a working version of GCC and precompiled  versions of the SPEC 95 benchmark suite.  SimpleScalar comes with several different simulators, each of which supports a different level of simulation: everything from timing-free but fast simulation (for debugging), to a full out-of-order simulator.  The simulated processor is a variant of the MIPS architecture.

Other Resources

Acknowledgments

The lecture notes have incorporated course materials developed by:

Louisiana State University Department of Computer Sciences